Read channel devices serve as interfaces between a hard disk on which digital information is stored and external devices (e.g., Central Processing Unit (CPU)) which receive and process the digital information in various applications. Read channel devices take the analog information stored as magnetic pulses on the hard disk drive and convert that information into digital values (i.e., “1”s and “0”s) that are readable by digital devices, such as a CPU.
Timing recovery is an important aspect of many read channel devices. Timing recovery systems serve to recover a clock signal at the symbol rate that is both phase-locked and frequency-locked to the incoming data (i.e., from the hard disk). A typical read channel device utilizes a digital phase lock loop (DPLL) to perform timing recovery operations. A typical DPLL uses a phase detector to extract phase error information from the incoming signal. A loop filter filters the output of the phase detector using two integrators: a frequency register integrator, and a phase register integrator (e.g., Voltage Controlled Oscillator (VCO)).
A read channel device, such as the type used for reading information from a disk drive, generally operates as follows. An analog ‘readback’ signal (corrupted by noise) from a magnetic recording head (of a disk drive or other device) is first equalized to a partial response (PR) channel through filtering. The analog waveform generated by the PR equalizer is then sampled at a T sampling rate provided by the timing circuit to produce an analog sample. That analog sample is then digitized using an Analog to Digital (A/D) converter to obtain a digital output signal. The digital output of the A/D converter is often referred to as the ‘Y’ signal (See signal YkT in FIG. 4 of the present application).
In the case of perfect equalization, perfect timing and generally perfect conditions, the above-described concept would be similar to passing random bits through a filter. For example, consider the PR channel to be filter having the filter coefficients [1 0−1]. Then, if random bits in the form [1 1−1−1 1 1 1 1−1−1] are passed to the PR channel, the output of the PR channel (which is obtained by convolving the input with channel filter) is then [−2−2 2 2 0 0−2−2]. This output is the uncorrupted ‘Y’ signal. That is, this is the signal obtained by equalizing the perfect ‘readback’ signal to a [1 0−1] PR channel, and then sampling and digitizing.
Note that for exemplary PR channel described above, the output levels are either 2, −2 or 0. These specific levels are often referred to as ‘eye’ levels. Often times, noise or other imperfections in the PR channel cause the digital output to contain values other than the ideal values. It should also be noted that the output of the exemplary PR channel (e.g., [1 0−1]) depends on the two previous bits, and the current bit, and hence has a memory of 2. Also, since the readback signal is almost always corrupted by noise, the obtained ‘eye’ levels will almost never be ideal. For example, a digital output of [−4−1 2 0 1−1−3−2] may be what is actually obtained, as opposed to the perfect output response (e.g., [−2−2 2 2 0 0−2−2]).
The difference between the actual A/D digital output signal (‘Y’) and the ideal ‘eye’ level (perfect or uncorrupted ‘Y’. sometimes referred to as ‘Y1’) is often termed as the error signal (E_N). In order to determine this difference, the actual A/D digital output signal must be compared to an ideal digital output signal. One way to generate an ideal digital output signal is by passing the actual A/D digital output signal to a detector, such as a Viterbi detector. The Viterbi detector takes the actual digital output signal (e.g., the signal from the A/D converter) and produces an estimation of the actual data bits (e.g., 1s or −1s). Since the Viterbi detector only estimates the actual data bits based on the A/D output signal, it will be noted that errors may occur when the detector does not estimate correctly. Once the actual data bits are known they can be convolved with the PR channel filter to obtain the ideal ‘eye’ levels. This output of the ideal ‘eye’ levels is often termed ‘Y1’ (See signal Y1kT in FIG. 4 of the present application). Of course, if the Viterbi detector makes errors in detecting the bits, the wrong ideal levels may be, obtained. Those of ordinary skill in the art will recognize that the more advanced detector, the better the decisions will be.
In a decision directed timing loop (such as the one described herein), decisions from the Viterbi detector (or other detector) are used to compute the bits, and hence the ideal levels and the error for the timing loop.
Another signal commonly referred to as a ‘SLOPE’ signal (See FIG. 1 of the present application) is also generated in the same manner as the ‘Y1’ signal discussed above (e.g., using a Viterbi detector to estimate the actual data bits). Again, only if the Viterbi detector detects the bits correctly will the ‘SLOPE’ signal be correct.
FIG. 1 shows a conventional digital phase lock loop (DPLL) circuit 100 for a read channel device. As shown, the DPLL circuit 100 includes a first multiplier 105 which receives an error signal E_N and a SLOPE signal from a Viterbi detector, and produces a phase error signal PE at its output. The PE signal is then input to second and third multipliers 110, 115. The second multiplier 110 also has a Frequency Gain signal input, and the third multiplier 115 also has a Phase Gain signal input. The output of the second multiplier 110 is transmitted to a first summer 120, and the output of the third multiplier is transmitted to a first adder 125. The first summer 120 takes the output of the second multiplier, and an output of a frequency register 130, and produces an output which is fed to the frequency register 130. The first adder 125 takes the output of the third multiplier 115, and an output of a frequency register 130, and produces an output which is fed to a second summer 135. The second summer 135 takes this signal, as well as an output signal from a phase register 140, and produces an output which is fed to the phase register 140. The output of the phase register 140 is then transmitted to a phase mixer 145. Finally, the phase mixer provides an output signal to control a voltage controlled oscillator (VCO).
In operation, the digital phase lock loop circuit 100 described above receives the error signal E_N, and modulates a control signal of a VCO so that a phase error is minimized. In particular, a Mean Squared Error (MSE) (computed by squaring each value of the signal E_N, and taking the average over all values) is minimized by the DPLL 100 of the present invention.
The DPLL 100 described above preferably includes a slope-based phase detector (PD). Slope-based phase detectors are also often referred to as Minimum Mean Squared Error Phase Detectors. It will be noted by those skilled in the art that other types of phase detectors exist and are also commonly used in DPLLs. Such other phase detectors include Maximum Likelihood Phase Detectors and Mueller and Muller (‘M&M’) Phase Detectors.
It is important that read channel devices have the ability to perform timing recovery at very low signal-to-noise ratios (SNRs). When a DPLL is unable to track an incoming waveform to provide accurate estimates of the sampling clock, various errors can occur in the received data. These errors often occur in bursts when the DPLL is not tracking the incoming waveform. These bursts occur because when the DPLL looses track of the incoming signal, the DPLL may not be able to reacquire the frequency and phase lock. These types of events are termed loss of lock (LOL) events.
Many conventional timing recovery systems operate utilizing a phase detector with a slope look-up table for determining the ideal waveform characteristics. The phase error produced by the phase detector is proportional to the product of the signal slope at the sampling instant and the error between the sampled value and the ideal value. The ideal value is the value corresponding to the perfectly equalized and perfectly sampled signal (at the symbol rate) without any noise or other imperfections. The read channel device employs a maximum likelihood Viterbi sequence detector algorithm to detect the data. In a decision directed loop, the ideal values at the symbol rate can be estimated by using the data stream itself, or by using earlier decisions from the sequence detector to avoid latency in obtaining the timing updates. After applying proper gains to the phase error, it is filtered by the loop filter using the frequency and phase integrators. The digital output of the loop filter controls an analog VCO which is capable of adjusting the sampling instant of the clock. The LOL performance strongly depends on the quality of the estimated ideal values. Better LOL performance is achieved by using accurate later decisions (with latency) in the sequence detector instead of using less accurate earlier decisions (without latency) to estimate the ideal sample values.
When a timing recovery system as described above is tracking the incoming waveform, the sampling instants will be very close to the ideal sampling instant. Thus, when a LOL event is about to happen, the sampling phase of the recovered clock drifts in one direction or the other from the ideal sampling instant.
Thus, there is currently a need for a timing recovery system which detects the direction and amount of this drift, and which uses this information to prevent a Loss of Lock event.